Active standard | Published: 28/11/2018

IEC 63011-3-ed.1.0

Integrated circuits - Three dimensional integrated circuits - Part 3: Model and measurement conditions of through-silicon via
(Circuits integres - Circuits integres tridimensionnels - Partie 3: Modele et conditions de mesure des trous de liaison a travers le silicium)

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Detail information

Designation: IEC 63011-3-ed.1.0

Publication date: 28/11/2018

Pages: 28

Country: International technical standard

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Anotation

IEC 63011-3:2018 specifies a reference model of through-silicon via (TSV) electrical characteristics required for an interface design in three dimensional integrated circuit (3-D IC) to transmit and receive digital data and measurement conditions for resistance and capacitance to specify TSV characteristics in 3-D IC. Power devices, RF devices and micro-electromechanical systems (MEMS) are not in the scope of this document. LIEC 63011-3:2018 specifie un modele de reference des caracteristiques electriques des trous de liaison a travers le silicium (TSV: through-silicon via) exigees pour la conception dune interface dans un circuit integre tridimensionnel (3-D IC) pour transmettre et recevoir des donnees numeriques, ainsi que les conditions de mesure de la resistance et de la capacite afin de specifier les caracteristiques des TSV dans un circuit integre tridimensionnel. Les dispositifs de puissance, les dispositifs aux frequences radioelectriques (RF) et les systemes microelectromecaniques (MEMS) ne font pas partie du domaine dapplication du present document.

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