Active standard | Published: 15/12/2004

ISO/IEC 18372-ed.1.0

Information technology - RapidIO TM interconnect specification

Available languages: English

Available design: electronic design (pdf), CD-ROM

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Detail information

Designation: ISO/IEC 18372-ed.1.0

Publication date: 15/12/2004

Pages: 399

Country: International technical standard

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Anotation

The electronic version of this International Standard can be downloaded from the ISO/IEC Information Technology Task Force (ITTF) web site. The RapidIO architecture was developed to address the need for a high-performance low pin count packet-switched system level interconnect to be used in a variety of applications as an open standard. The architecture is targeted toward networking, telecom, and high performance embedded applications. It is intended primarily as an intra-system interface, allowing chip-to-chip and board-to-board communications at Gigabyte per second performance levels. It provides a rich variety of features including high data bandwidth, low-latency capability and support for high-performance I/O devices, as well as providing globally shared memory, message passing, and software managed programming models.

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