UNE - Španělské národní normy

Mechanical standardization of semiconductor devices - Part 6-12: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guidelines for fine-pitch land grid array (FLGA) (Endorsed by AENOR in November of 2011.)

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Mechanical standardization of semiconductor devices - Part 6-13: Design guideline of open-top-type sockets for Fine-pitch Ball Grid Array (FBGA) and Fine-pitch Land Grid Array (FLGA) (Endorsed by Asociación Espanola de Normalización in January of 2017.)

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Mechanical standardization of semiconductor devices -- Part 6-16: Glossary of semiconductor tests and burn-in sockets for BGA, LGA, FBGA and FLGA (IEC 60191-6-16:2007). (Endorsed by AENOR in October of 2007.)

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Mechanical standardization of semiconductor devices - Part 6-17: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for stacked packages - Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-PFLGA) (Endorsed by AENOR in September of 2011.)

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Mechanical standardization of semiconductor devices -- Part 6-18: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for ball grid array (BGA) (Endorsed by AENOR in May of 2010.)

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Mechanical standardization of semiconductor devices -- Part 6-19: Measurement methods of the package warpage at elevated temperature and the maximum permissible warpage (Endorsed by AENOR in September of 2010.)

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Mechanical standardization of semiconductor devices -- Part 6-2: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for 1,50 mm, 1,27 mm and 1,00 mm pitch ball and column terminal packages

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Mechanical standardization of semiconductor devices -- Part 6-20: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of small outline J-lead packages (SOJ) (Endorsed by AENOR in February of 2011.)

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Mechanical standardization of semiconductor devices -- Part 6-21: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of small outline packages (SOP) (Endorsed by AENOR in February of 2011.)

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Mechanical standardization of semiconductor devices - Part 6-22: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for semiconductor packages Silicon Fine-pitch Ball Grid Array and Silicon Fine-pitch Land Grid Array (S-FBGA and S-FLGA) (Endorsed by AENOR in April of 2013.)

Dostupné jazyky: Anglicky

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