Aktívna norma | Vydaná: 19.05.2011

IEEE/IEC 62530-2011

SystemVerilog -- Unified Hardware Design, Specification, and Verification Language

Dostupné jazyky: Anglicky

Dostupné prevedenie: Zabezpečené PDF - okamžité stiahnutie, Tlačené

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Podrobné informácie

Označenie: IEEE/IEC 62530-2011

Dátum vydania: 19.05.2011

Stránok: 1294

Krajina: Medzinárodná technická norma

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Anotácia

- Active.
This standard represents a merger of two previous standards: IEEE Std 1364™-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.

ISBN: 978-0-7381-6607-0, 978-0-7381-6633-9
Number of Pages: 1294
Product Code: STD97095, STDPD97095
Keywords: assertions, design automation, design verification, hardware description language, HDL, HDVL, PLI, programming language interface, SystemVerilog, Verilog, VPI
Category: Aerospace

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