Aktívna norma | Vydaná: 22.11.2005

IEEE 1800-2005

IEEE Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language

Dostupné jazyky: Anglicky

Dostupné prevedenie: Zabezpečené PDF - okamžité stiahnutie

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Podrobné informácie

Označenie: IEEE 1800-2005

Dátum vydania: 22.11.2005

Stránok: 0

Krajina: Medzinárodná technická norma

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Anotácia

New IEEE Standard - Superseded.
This standard represents a merger of two previous standards: IEEE 1364-2005 Verilog hardware description language (HDL) and IEEE 1800-2005 SystemVerilog unified hardware design, specification and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard enables users to have all information regarding syntax and semantics in a single document.

ISBN: 978-0-7381-4811-3
Number of Pages: 648
Product Code: STDRE95376
Keywords: Assertions, Design Automation, Design Verification, Hardware Description Language (HDL), Verilog, Programming Language Interface (PLI), Verilog Programming Interface (VPI), SystemVerilog
Category: Design Automation

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