ČSN - Czech national standards

Behavioural languages - Part 3-2: Mathematical operation in VHDL

Available design: Print design

Behavioural languages - Part 3-3: Synthesis in VHDL

Available design: Print design

Design automation - Part 1: Standard test language for all systems - Common abbreviated test language for all systems (C/ATLAS)

Available languages: Czech preface only

Available design: Print design

Electronic Design Interchange Format (EDIF) - Part 1: Version 3 0 0

Available languages: Czech preface only

Available design: Print design

Electronic Design Interchange Format (EDIF) - Part 2: Version 4 0 0

Available languages: Czech preface only

Available design: Print design

Specification for the representation of Quality rules and metrics for Hardware and Software Design Languages

Available design: Print design

Electronic design automation libraries - Part 1: Input/Output buffer information specifications (IBIS version 3.2)

Available design: Print design

Delay and power calculation standards - Part 1: Integrated circuit delay and power calculation systems

Available design: Print design

Delay and power calculation standards - Part 2: Pre-layout delay calculation specification for CMOS ASIC libraries

Available design: Print design

Graphical symbols for use on equipment - Part 1: Overview and application

Available design: Print design