Active standard | Published: 11/10/2023

IEC 61523-1-ed.3.0

Delay and power calculation standards - Part 1: Integrated Circuit (IC) Open Library Architecture (OLA)

Available languages: English

Available design: electronic design (pdf), CD-ROM

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Detail information

Designation: IEC 61523-1-ed.3.0

Publication date: 11/10/2023

Pages: 0

Country: International technical standard

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Anotation

IEC 61523-1:2023 focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity. The standard specifications covered in this document are as follows: - Description language for timing and power modeling, called the “delay calculation language” (DCL) - Software procedural interface (PI) for communications between EDA applications and compiled libraries of DCL descriptions - Standard file exchange format for parasitic information about the chip design: Standard Parasitic Exchange Format (SPEF) - Informative usage examples - Informative notes. This is an IEC/IEEE dual logo standard.

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