Active standard | Published: 28/11/2018

IEC 63011-1-ed.1.0

Integrated circuits - Three dimensional integrated circuits - Part 1: Terminology
(Circuits integres - Circuits integres tridimensionnels - Partie 1 : Terminologie)

Available languages: English and French

Available design: electronic design (pdf), Print design, CD-ROM

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Detail information

Designation: IEC 63011-1-ed.1.0

Publication date: 28/11/2018

Pages: 24

Country: International technical standard

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Anotation

IEC 63011-1:2018 provides definitions pertaining to multichip integrated circuits, as vertically stacked dies using through-silicon vias (TSVs) or micro bumps. Terms and definitions related to the fabrication and test of the multichip integrated circuits are also provided. LIEC 63011-1:2018 donne des definitions relatives aux circuits integres multipuces constitues de puces empilees verticalement a laide de trous de liaison a travers le silicium ou de microbosses. Des termes et definitions relatifs a la fabrication et aux essais des circuits integres multipuces sont egalement fournis.

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