STN - Slovenské národní normy

Designation of phase differences by hour numbers in three-phase AC systems

Dostupné jazyky: Anglicky

Dostupné prevedenie: Tlačené

Delay and power calculation standards -- Part 2: Pre-layout delay calculation specification for CMOS ASIC libraries

Dostupné jazyky: Anglicky

Dostupné prevedenie: Tlačené

Delay and power calculation standards -- Part 1: Integrated circuit delay and power calculation systems

Dostupné prevedenie: Tlačené

Design automation. Part 1: VHDL language reference manual

Dostupné prevedenie: Tlačené

Behavioural languages. Part 2: VHDL multilogic system for model interoperability

Dostupné prevedenie: Tlačené

Behavioural languages. Part 3-2: Mathematical operation in VHDL

Dostupné prevedenie: Tlačené

Behavioural languages. Part 3-3: Synthesis in VHDL

Dostupné prevedenie: Tlačené

Design automation. Part 1: Standard test language for all systems. Common abbreviated test language for all systems (C/ATLAS)

Dostupné jazyky: Anglicky

Dostupné prevedenie: Tlačené

Electronic Design Interchange Format (EDIF). Version 3 0 0 (IEC 61690- 1:2000)

Dostupné jazyky: Anglicky

Dostupné prevedenie: Tlačené

Electronic Design Interchange Format (EDIF). Part 2: Version 4 0 0 (IEC 61690-2:2000)

Dostupné jazyky: Anglicky

Dostupné prevedenie: Tlačené